assign la=~a_reg;
assign oa={a_reg[15:0],1'b0};
assign wa={a_reg[15:0],2'b00};
assign ta={a_reg[15:0],3'b000};
case(b_reg[2:0])
3'b0:
begin
a_reg1<=0;
b_reg1<=0;
end
3'b001:
begin
a_reg1<=0;
b_reg1<=a_reg;
end
3'b010:
begin
a_reg1<=0;
b_reg1<=oa;
end
3'b100:
begin
a_reg1<=wa;
b_reg1<=0;
end
3'b011:
begin
a_reg1<=oa;
b_reg1<=a_reg;
end
3'b101:
begin
a_reg1<=wa;
b_reg1<=a_reg;
end
3'b110:
begin
a_reg1<=wa;
b_reg1<=oa;
end
3'b111:
begin
a_reg1<=d_reg;
b_reg1<=0;
end
endcase
华莱氏树：
wallace w1(a_reg1[0],b_reg1[0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,c11[0],c12[0],c13[0],c14[0],c21[0],c22[0],c23[0],c31[0],c32[0],c41[0],c51[0],
1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s41[0]);
wallace w2(a_reg1[1],b_reg1[1],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,c11[1],c12[1],c13[1],c14[1],c21[1],c22[1],c23[1],c31[1],c32[1],c41[1],c51[1],
c11[0],c12[0],c13[0],c14[0],c21[0],c22[0],c23[0],c31[0],c32[0],c41[0],s41[1]);
wallace w3(a_reg1[2],b_reg1[2],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,c11[2],c12[2],c13[2],c14[2],c21[2],c22[2],c23[2],c31[2],c32[2],c41[2],c51[2],
c11[1],c12[1],c13[1],c14[1],c21[1],c22[1],c23[1],c31[1],c32[1],c41[1],s41[2]);
wallace w4(a_reg1[3],b_reg1[3],a_reg2[0],b_reg2[0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,c11[3],c12[3],c13[3],c14[3],c21[3],c22[3],c23[3],c31[3],c32[3],c41[3],c51[3],
c11[2],c12[2],c13[2],c14[2],c21[2],c22[2],c23[2],c31[2],c32[2],c41[2],s41[3]);
........
wallace w23(1'b0,1'b0,1'b0,1'b0,a_reg3[16],b_reg3[16],a_reg4[13],b_reg4[13],a_reg5[10],b_reg5[10],1'b0,a_reg6[7],c11[22],c12[22],c13[22],c14[22],c21[22],c22[22],c23[22],c31[22],c32[22],c41[22],c51[22],
c11[21],c12[21],c13[21],c14[21],c21[21],c22[21],c23[21],c31[21],c32[21],c41[21],s41[22]);
wallace w24(1'b0,1'b0,1'b0,1'b0,a_reg3[17],1'b0,a_reg4[14],b_reg4[14],a_reg5[11],b_reg5[11],1'b0,a_reg6[8],c11[23],c12[23],c13[23],c14[23],c21[23],c22[23],c23[23],c31[23],c32[23],c41[23],c51[23],
c11[22],c12[22],c13[22],c14[22],c21[22],c22[22],c23[22],c31[22],c32[22],c41[22],s41[23]);
........
wallace w31(1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,a_reg5[18],1'b0,1'b0,a_reg6[15],c11[30],c12[30],c13[30],c14[30],c21[30],c22[30],c23[30],c31[30],c32[30],c41[30],c51[30],
c11[29],c12[29],c13[29],c14[29],c21[29],c22[29],c23[29],c31[29],c32[29],c41[29],s41[30]);
wallace w32(1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,co[0],co[1],co[2],co[3],co[4],co[5],co[6],co[7],co[8],co[9],c51[31],
c11[30],c12[30],c13[30],c14[30],c21[30],c22[30],c23[30],c31[30],c32[30],c41[30],s41[31]);
五级华莱氏：
wallace(a,b,c,a1,b1,c1,a2,b2,c2,a3,b3,c3,c11,c12,c13,c14,c21,c22,c23,c31,c32,c41,c51,
ic11,ic12,ic13,ic14,ic21,ic22,ic23,ic31,ic32,ic41,s51);
input a,b,c,a1,b1,c1,a2,b2,c2,a3,b3,c3,ic11,ic12,ic13,ic14,ic21,ic22,ic23,ic31,ic32,ic41;
output c11,c12,c13,c14,c21,c22,c23,c31,c32,c41,c51,s51;
wire s11,s12,s13,s14,s21,s22,s23,s32,s31,s41,s51;
fulladd m1(a,b,c,s11,c11);
fulladd m2(a1,b1,c1,s12,c12);
fulladd m3(a2,b2,c2,s13,c13);
fulladd m4(a3,b3,c3,s14,c14);
fulladd m5(1'b0,ic11,s11,s21,c21);
fulladd m6(ic12,s12,ic13,s22,c22);
fulladd m7(s13,ic14,s14,s23,c23);
fulladd m8(ic21,s21,ic22,s31,c31);
fulladd m9(s22,ic23,s23,s32,c32);
fulladd m10(s31,ic32,s32,s41,c41);
fulladd m11(ic31,ic41,s41,s51,c51);
endmodule
module fulladd(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign {cout,sum}=a+b+cin;
endmodule