linear-feedback-shift-register

下面是一个八位的伪随机数产生的verilog文件，我想够用了。

// DEFINES

`timescale 1ns/1ns

`define DEL1// Clock-to-output delay. Zero

// time delays can be confusing

// and sometimes cause problems.

// These are good tap values for 2 to 32 bits

`define TAP22'b11

`define TAP33'b101

`define TAP44'b1001

`define TAP55'b10010

`define TAP66'b100001

`define TAP77'b1000001

`define TAP88'b10001110

`define TAP99'b100001000

`define TAP1010'b1000000100

`define TAP1111'b10000000010

`define TAP1212'b100000101001

`define TAP1313'b1000000001101

`define TAP1414'b10000000010101

`define TAP1515'b100000000000001

`define TAP1616'b1000000000010110

`define TAP1717'b10000000000000100

`define TAP1818'b100000000001000000

`define TAP1919'b1000000000000010011

`define TAP2020'b10000000000000000100

`define TAP2121'b100000000000000000010

`define TAP2222'b1000000000000000000001

`define TAP2323'b10000000000000000010000

`define TAP2424'b100000000000000000001101

`define TAP2525'b1000000000000000000000100

`define TAP2626'b10000000000000000000100011

`define TAP2727'b100000000000000000000010011

`define TAP2828'b1000000000000000000000000100

`define TAP2929'b10000000000000000000000000010

`define TAP3030'b100000000000000000000000101001

`define TAP3131'b1000000000000000000000000000100

`define TAP3232'b10000000000000000000000001100010

`define BITS 8// Number of bits in the LFSR

`define TAPS `TAP8// This must be the taps for the

// number of bits specified above

`define INIT 1// This can be any non-zero value

// for initialization of the LFSR

// TOP MODULE

modulerandom_number(

data);

// INPUTS

//inputclk;// Clock

//inputreset;// Reset

// OUTPUTS

output [`BITS-1:0]data;// LFSR data

// INOUTS

// SIGNAL DECLARATIONS

regclk;

regreset;

reg [`BITS-1:0] data;

// PARAMETERS

initial

begin

reset=0;

#4 reset=1;

#2 reset=0;

end

// ASSIGN STATEMENTS

initial

clk=0;

always

clk= #1 ~clk;

// MAIN CODE

// Look at the rising edge of clock or reset

always @(posedge clk or posedge reset) begin

if (reset)

data <= #`DEL `INIT;

else begin

// Shift all of the bits left

data[`BITS-1:1] <= #`DEL data[`BITS-2:0];

`ifdef ADD_ZERO// Use this code if data == 0 is required

// Create the new bit 0

data[0] <= #`DEL ^(data & `TAPS) ^ ~|data[`BITS-2:0];

`else// Use this code for a standard LFSR

// Create the new bit 0

data[0] <= #`DEL ^(data & `TAPS);

`endif

end

end

initial

#1000 $finish;

endmodule// LFSR