加法器源程序 module counter (count, clk, reset); output [7:0] count; input clk, reset; reg [7:0] count; parameter tpd_clk_to_count=1; parameter tpd_reset_to_count =1; function [7:0] increment; input [7:0] val; reg [3:0] i; reg carry; begin increment = val; carry = 1'b1; /* * Exit this loop when carry == ze ..
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